(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to novel lateral PNP and NPN bipolar transistor structures with increased current gain and a method of fabrication. The process is compatible with CMOS processes for making BiCMOS integrated circuits.
(2) Description of the Prior Art
Bipolar and Complementary Metal-Oxide Semi-conductor (CMOS) devices can be built on the same substrate to form BiCMOS circuits. These BiCMOS circuits provide additional advantages over either bipolar or CMOS circuits built separately on the same substrate. The bipolar transistor provides high current driver capabilities and is very useful as a constant current source and active load in many analog/digital applications. Alternatively, the CMOS devices composed of P and N-channel field effect transistors (NPN-FETs and PNP-FETs) offer low power consumption, high packing density, and dynamic memory storage capabilities. Unfortunately, the vertical bipolar transistors with high current gains (about 100) require more complex processing and increased manufacturing cost.
An alternative approach to using a conventional vertical bipolar transistor is to use a lateral PNP or NPN bipolar transistor which is more compatible with CMOS processing and still provides the constant current source and is very useful as an active load. The improved current-voltage (I-V) characteristics of the Lateral PNP bipolar transistor (also referred to as an L-PNP bipolar) are shown in FIG. 1 vs. the less desirable I-V characteristics of a P-channel FET (hereafter referred to as a PNP-FET) shown in FIG. 2. The comparison is for a lateral PNP bipolar having a 0.6 micrometer (um) base width and a PNP-FET having a 0.6 um channel length. As is clearly seen in FIG. 1, a family of I-V curves are shown for a series of constant base currents (I.sub.b), where the base currents are increased in increments of 1 microampere from 0 to 4 microamperes, as depicted respectively by the curves I.sub.b (0), I.sub.b (1), I.sub.b (2), I.sub.b (3), and I.sub.b (4) in FIG. 1. The I-V curves are shown for a collector current (I.sub.c) as a function of the applied collector bias voltage (V.sub.ce) between the collector-emitter where the I.sub.c is measured in microamperes along the vertical axis Y, and the V.sub.ce is measured in volts along the horizontal axis X. As can be seen, the I.sub.c increases rapidly as a function of increasing V.sub.ce and remains essentially constant thereafter. For example, I.sub.c is essentially constant when V.sub.ce is greater than 0.25 volts. On the other hand, the PNP-FET shown in FIG. 2 does not have a flat drain current (I.sub.D) region as a function of drain voltage (V.sub.D) and does not provide the ideal constant current capability. This is best illustrated in FIG. 2 by the family of I-V curves for a series of different gate voltages V.sub.G, where V.sub.G is varied in increments of 1.0 volts from 0 to 3 volts as depicted respectively by V.sub.G (0), V.sub.G (1), V.sub.G (2), and V.sub.G (3) in FIG. 2, and is held constant while the I.sub.D is plotted along the Y axis as a function of V.sub.D along the X axis. As is clearly seen by the family of curves, the I.sub.D varies significantly as a function of V.sub.D up to a V.sub.D of 5.0 volts, and therefore does not provide the desired constant current output.
However, the conventional L-PNP or L-NPN bipolar transistors have limitations, as is best described with reference to FIGS. 3A and 3B for a conventional prior art L-PNP bipolar transistor. One of these limitations is a substantially lower current gain (e.g. I.sub.c (L)/I.sub.b &lt;5, where I.sub.c (L) is the L-PNP collector current, and I.sub.b is the base current) for the L-PNP bipolar transistor. To best understand the reason for this low current gain, reference is made to FIG. 3A. A schematic cross-sectional view is shown for a conventional L-PNP bipolar transistor formed in a device area having an N.sup.- well 14 doped with arsenic or phosphorus on and in a P doped (boron) silicon substrate 10 and surrounded by a field oxide 12. This L-PNP is formed during fabrication of the FET by growing a gate oxide 16 and a polysilicon layer 18 which are patterned to leave portions over the intrinsic base region B formed from the N.sup.- well 14. Next an N.sup.++ base contact 17 is made to the N.sup.- well. The P.sup.++ emitter 20 and P.sup.++ collector 20' are then formed in the emitter area E and collector area C by ion implanting boron (B.sup.11), while the patterned polysilicon 18 serves as an implant blockout mask. Now as is clearly seen in FIG. 3A and depicted by the superimposed schematic diagram for the bipolar circuit elements V-PNP and L-PNP, the current gain of the L-PNP bipolar transistor is reduced because of the unwanted parasitic V-PNP bipolar portion of the lateral-PNP bipolar transistor between the emitter 20 and the substrate 10. This results in an unwanted V-PNP collector current I.sub.c (V) that reduces the desired collector current I.sub.c (L) of the L-PNP bipolar transistor, as depicted in FIG. 3B. Now as shown in FIG. 3B, when the emitter-base is forward biased (V.sub.be), the emitter current I.sub.e injected into the N.sup.- well 14 (which serves as the N base for the L-PNP) results in an unwanted parasitic collector current I.sub.c (V) in the substrate 10, which reduces the collector current I.sub.c (L) of the L-PNP transistor to the collectors 20' (FIG. 3A) resulting in low current gain.
One prior-art method of improving upon these L-PNP bipolar transistors, shown in FIG. 4, is to form a N.sup.+ region 11 in the P.sup.- substrate 10 followed by a P.sup.- epitaxial layer 13 (EPI) prior to forming the bipolar device. An N.sup.- well 14 is formed next in epitaxial layer 13 in which the L-PNP bipolar transistor is formed similar to the method of the prior art in FIG. 3A. This forms a heavily N.sup.+ doped region at the V-PNP bipolar base-collector junction 1 under the P.sup.++ emitter 20 to minimize the vertical PNP current gain thereby enhancing the lateral PNP current gain. However, this significantly reduces the reverse bias breakdown voltage at the base-collector junction 1. Also, minority carrier injection from the emitter 20 into the base area under the emitter 20 is not significantly reduced, which would further reduce the V-PNP current gain and increase the L-PNP current gain. The method also requires more processing steps that include growing a costly epitaxial layer and increases manufacturing cost.
One method of forming a lateral-PNP is described by Joyce et al., U.S. Pat. No. 5,326,710, in which devices having reduced parasitic capacitance between an N.sup.+ buried layer and an epitaxial layer are formed by implanting N wells prior to growing the epitaxial layer. The process also provides reduced geometries for improved performance. Another method for making lateral bipolar transistors is described by Cook et al., U.S. Pat. No. 5,187,109, in which an N.sup.+ epitaxy and an N.sup.- epitaxy are utilized for making an L-PNP bipolar transistor that is compatible with CMOS technology. A further method for making lateral bipolar transistors is described by Anantha et al. in U.S. Pat. No. 4,546,536. This method also uses an N.sup.- epitaxial layer grown on an N.sup.+ diffused layer in a P.sup.- silicon substrate, and provides a method for fabricating lateral NPN transistors with reduced base areas and an emitter over an insulating layer to reduce the parasitic capacitance. Anantha et al., U.S. Pat. No. 4,264,382, use a recessed oxide under a portion of a L-PNP or L-NPN to improve current gain. U.S. Pat. No. 4,167,425 issued to Herbst describes a method for making a lateral PNP bipolar transistor having a buried N.sup.+ layer and an N.sup.- epitaxial layer. The collector and emitter are then formed in the N.sup.- epitaxial layer over the buried N.sup.+ layer.
Therefore, there is still a strong need in the semiconductor industry to make L-PNP and L-NPN bipolar transistors with improved current gain, compatible with CMOS technology, and at low manufacturing cost.